Conventionally, there has been known a semiconductor integrated circuit using pipeline processing in which data transmission between stages that perform predetermined signal processing is performed in synchronization with a clock signal.
Between the stages, the data transmission is performed through a data transmission path while the clock signal transmission is performed through a clock signal transmission path. There is a problem, however, that power consumption in the data transmission path or the clock signal transmission path becomes larger as scale of integration of the semiconductor integrated circuit becomes larger.